Silicon Sovereignty: Execution Over Subsidies

Silicon sovereignty is a decade of execution, not a subsidy line

China's LineShine hit 1.54 exaflops under US export controls. India's ISM 2.0 has ₹1,000 crore. The gap isn't money — it's an integrated stack that took twelve years to build.

On June 25, 2026, Nature confirmed that a Chinese Armv9-based system called LineShine — sitting in the National Supercomputing Center in Shenzhen — had displaced the American El Capitan atop the global supercomputer ranking, sustaining 1.54 exaflops on its own domestically-designed LX2 processors. That is the number policymakers in New Delhi should stare at, because it was produced under four years of tightening US export controls and without a single Nvidia GPU. The lesson is not that subsidies work — it is that a vertically integrated silicon stack, patiently built across design, tooling, materials and interconnects, defeats a chokepoint strategy that a fab alone cannot. India's ISM 2.0, announced this February with ₹1,000 crore for FY 2026-27, is still choosing between the two.

What LineShine actually proves

Read the LineShine paper on arXiv and the pattern is unmistakable. The system runs 20,480 nodes of Armv9-based LX2 processors, each delivering 60.3 TFLOP/s in FP64 and 240 TFLOP/s in BFloat16, stitched together by a proprietary "LingQi" interconnect at 1.6 Tb/s per node, according to the arXiv preprint documenting the machine's exascale training run. That is not a fab story. It is a domestic instruction-set-architecture story, a domestic packaging story, a domestic HBM story and a domestic network fabric story — the layers Western analysts spent a decade insisting China could never assemble under sanctions.

The US Congressional Research Service traces the controls back to 2018 and BIS's October 2022 and October 2023 rules, which tightened licence requirements for advanced logic, EDA tools, and lithography equipment destined for entities in Country Group D:5, codified at 15 CFR § 744.23. Beijing's response was not to bid harder for Nvidia chips. It was to fund substitutes at every layer through three tranches of the "Big Fund" — CNY 686 billion since 2014, according to MERICS, with the third tranche of $47.5 billion alone concentrated on chokepoint hardware, per Caixin via Institut Montaigne. LineShine is the compounding return on that stack.

Beijing has also just told markets it will keep paying. China's 15th Five-Year Plan, formally adopted by the National People's Congress on March 12, 2026, calls for "extraordinary measures" to secure breakthroughs in integrated circuits, foundational software and semiconductor manufacturing equipment, according to the Congressional Research Service brief on the plan. Bruegel notes that semiconductors are designated a "pillar industry" and AI is treated as a vertically integrated state project spanning models, chips, cloud and applications. Bloomberg, cited by MERICS, reports another CNY 500 billion in additional subsidies is planned specifically for semiconductor firms over the plan period. Breakthroughs in 3–5 nm and 7–10 nm are explicit targets.

India's stack is real. The clock is not the same clock.

None of this makes India's position hopeless — it makes the metric different. India already hosts roughly 20% of the global semiconductor design workforce, according to a May 2026 NITI Aayog paper on the future of India's chip industry. The Tata Electronics fab at Dholera, backed by ₹91,526 crore and a technology partnership with Taiwan's Powerchip (PSMC), is moving from paper to plant: India's Press Information Bureau confirmed on a JBIC delegation visit that the 163-acre facility will begin production in 2027 at 50,000 wafers per month across 110–28 nm nodes. Tata's May 2026 MoU with ASML added the missing lithography link. Carnegie's Konark Bhandari argued in June that ASML's decision is itself a market signal: the Indian ecosystem has now reached "critical mass" — Tokyo Electron, Merck Electronics, ROHM and Intel have all signed adjacent deals.

The compute layer is likewise moving. The PIB brief on IndiaAI records more than 38,000 GPUs onboarded at a subsidised ₹65/hour rate, with Union Minister Ashwini Vaishnaw announcing a further 20,000 GPUs at the India-AI Impact Summit on February 17, 2026. The National Supercomputing Mission has now deployed AIRAWAT and PARAM Siddhi-AI across more than 40 petaflops of capacity and has explicitly reoriented indigenous processor work onto the open RISC-V ISA, per a June 2026 MeitY release. A Design Linked Incentive scheme has taped out 16 chip designs, seven of them already fabricated at TSMC nodes as advanced as 12 nm.

But the honest picture — as the Bengaluru-based Takshashila Institution reminded readers in its February 2026 budget analysis — is that ISM 1.0's disbursals badly trail its announcements. "Despite the budgeted allocations for the Dholera fab in FY24 and FY25, not a single penny was disbursed," analyst Pranay Kotasthane wrote; the FY26 revised estimate was again substantially below plan. The ATMP segment (assembly, testing, marking, packaging) is moving; front-end fabrication is behind schedule; SCL Mohali's modernisation is "more promise than reality"; and the design incentive structure remains poorly tuned to the country's actual strength — fabless start-ups such as InCore, Vervesemi and iVP.

The non-obvious angle: the leverage is in the layer no one funded

Here is where India's strategic instinct is wrong, and where China's is right. Both governments frame silicon sovereignty as a fab-count problem. But the LineShine chip was not, in the first instance, a fab achievement. It was an architecture and interconnect achievement. The LX2 processor is Armv9 with proprietary SVE/SME extensions; the LingQi network is proprietary; the software stack is co-optimised across compilers, memory hierarchy and runtime — a companion arXiv paper on billion-parameter interatomic potentials shows LineShine hitting 1.2 EFLOPS at 90.3% parallel efficiency on its own PyTorch 2.10 + KML BLAS stack, without touching a Western GPU library.

That is the layer where India's 20% share of the global design workforce could compound — if state capital rewarded it. It does not. NITI Aayog's own May 2026 industry paper puts the cumulative capital India needs at $135–180 billion over the coming decade, spread across design, fabrication, advanced packaging and materials, and says the government should commit at least a third to de-risk projects. ISM 2.0's ₹1,000 crore for FY 2026-27 — roughly $115 million — is a rounding error on that number. As the Observer Research Foundation's Operationalising India's Sovereign AI Stack argued in June, "as performance gains increasingly derive from advanced packaging, chiplet integration, and testing rather than node shrinkage, system-level optimisation becomes decisive." That is a policy sentence pointing at where the marginal rupee earns most.

Washington's zig-zag is India's window

The second-order beneficiary of America's inconsistency has quietly become New Delhi. On January 15, 2026, BIS issued a rule allowing case-by-case exports of Nvidia H200 and AMD MI325X to PRC end users, subject to third-party lab testing and a 25% import tariff — the so-called "Chips Arrangement" described in a January 2026 CRS legal sidebar. By June, Al Jazeera reported BIS was walking back interpretation on Chinese-headquartered subsidiaries buying chips abroad. MIT's Center for International Studies warned in June 2026 that the credibility of the entire allied export-control regime is being eroded by such policy signals.

For Beijing, the message is straightforward: keep building substitutes, because access is negotiable. For New Delhi, the message is more interesting. India can now credibly pitch itself as the "trusted" trailing-edge node manufacturer — DUV lithography, 28–110 nm, automotive, industrial and telecom — precisely the segment Carnegie identifies as ASML's expanding market. But that pitch survives only if the ecosystem — equipment, materials, EDA, packaging — matures around Dholera before global overcapacity in mature nodes arrives. The Swedish Institute of International Affairs warns that China's plan is deliberately engineered to make next-generation semiconductors "sources of tomorrow's global overcapacity," on the solar-and-EV pattern. That is the deadline hidden inside India's silicon window.

Diplomat View

The forecast: India's Dholera fab will begin trial production on schedule in late 2027 and reach commercial ramp in 2028, but ISM 2.0's ₹1,000 crore FY27 outlay will be revised upward — likely doubled or tripled — inside the next two Union Budgets, once MeitY confronts the NITI Aayog $135–180 billion gap in writing. The genuinely differentiated Indian play, however, will not be the fab. It will be a chiplet-and-packaging cluster anchored on RISC-V processor IP and India's fabless design bench, sold to trailing-edge global customers frozen out of Chinese supply. That is where sovereignty is bought — in the layer LineShine actually depended on, and the layer India already half-owns.

What would revise this call: a Dholera slippage past 2028, a formal MATCH Act aligning DUV controls against India as well as China, or a collapse in the DLI scheme's chip tape-out cadence below its current pace. Any one of those and the "trusted trailing-edge" pitch dies before it earns customers.

What to watch next

• Union Budget, Feb 1, 2027: whether ISM 2.0's FY 2027-28 allocation crosses ₹10,000 crore — the minimum credible signal of sustained state commitment.
• Dholera first-silicon milestone, mid-2027: pilot wafers from the Tata-PSMC line; slippage past Q4 2027 would compress the entire trailing-edge window.
• US Congress on the MATCH Act, session ending Jan 2027: passage would extend DUV controls beyond China and could catch India in the net.

The Bottom Line

Silicon sovereignty is a compounding asset, not a subsidy line. China's LineShine exaflop was produced by a decade of coordinated investment across design, tooling, interconnects and software — not by a bigger cheque in any single year. India has the design talent and the diplomatic window to build the same stack around trailing-edge nodes and RISC-V, but only if ISM 2.0 stops behaving like a fab-count programme and starts funding the layers — packaging, EDA, chiplet integration, indigenous IP — where its 20% share of the world's chip designers can actually compound.