Dongfang Suanxin's 3D-Stacked Bet Against US

Dongfang Suanxin's 3D-Stacked Bet Against US Chip Curbs

Shanghai startup Dongfang Suanxin exited stealth on July 1, 2026, wagering that 3D chip stacking and software-defined architecture can neutralize US semiconductor export controls.

On July 1, 2026, a Shanghai-based AI chip startup called Dongfang Suanxin exited stealth after two years of quiet operation, and the technology it disclosed is aimed squarely at the seams of the US export-control regime. Its flagship DF1000 accelerator combines a "software-defined chip" architecture with 3D-stacked near-memory computing, built end-to-end on a domestic supply chain — a design that treats Washington's controls on advanced lithography and high-bandwidth memory (HBM) not as an obstacle to overcome but as an obsolete framework to route around. The thesis worth taking seriously is that packaging, not process node, is now the axis on which the US-China chip contest turns — and the DF1000 is the clearest signal yet that Beijing has internalized it.

Dongfang Suanxin is not a garage operation. It employs more than 500 staff across seven cities and is chaired by Wei Shaojun, a Tsinghua University microelectronics professor and vice-president of the China Semiconductor Industry Association, according to the South China Morning Post. Its cap table includes the state-backed National AI Industry Investment Fund, Jack Ma's Yunfeng Capital, and the venture arms of Xiaomi and JD.com, per reporting by tech360tv. It is, in other words, a state-adjacent industrial project chaired by a man who helps write China's semiconductor policy — the kind of construct that in the West would be called strategic industrial planning and in Beijing is simply Tuesday.

Why 3D stacking is a control-regime problem

Every meaningful US chip control since October 2022 has been calibrated to two variables: transistor density (a proxy for lithography node) and off-chip memory bandwidth (a proxy for HBM). The Bureau of Industry and Security's January 15, 2025 Framework for Artificial Intelligence Diffusion extended those thresholds worldwide under ECCNs 3A090.a and 4A090.a, and imposed a new control on AI model weights themselves under a newly-created ECCN 4E091. A companion interim final rule issued the following day added a foreign-produced direct product rule for HBM specifically, closing the transshipment path through which Chinese firms had been sourcing SK Hynix and Samsung stacks via foreign subsidiaries. The theory: if China cannot buy sub-7nm EUV tools or HBM3E stacks, it cannot build a competitive AI accelerator.

3D stacking with hybrid bonding attacks both premises simultaneously. By vertically stacking DRAM dies directly onto a logic die through copper-to-copper bonds at sub-10-micron pitch, Chinese designers can achieve I/O density roughly two orders of magnitude higher than HBM at 110,000 connections per square millimeter, according to research from Peking University and Xi'an UniIC published on arXiv. The same work documents per-bit memory-access energy of 0.66 to 0.88 picojoules — a 77% to 83% reduction versus HBM. Wei's near-memory approach therefore does not need HBM3E at all; it needs a mature DRAM node (which CXMT can produce) and an advanced packaging line (which SiCarrier and JCET can deliver). The lithography constraint that anchors the entire US control architecture becomes a second-order problem.

The "software-defined chip" half of the design compounds the effect. It is the commercial expression of a decade of Tsinghua research — including work by Wei's frequent collaborator Shouyi Yin on reconfigurable hybrid neural network processors, catalogued on Google Scholar and dating to at least the 2017 "1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor" paper. A single die can be reconfigured at runtime to look like a training accelerator, an inference engine, or a sparse-matrix processor, letting Chinese fabs amortize one mature-node design across the workloads Nvidia currently addresses with a portfolio of A100/H100/H200/B200 variants. Academic work on the frontier — such as the MINISA reconfigurable inference architecture presented at IEEE ISPASS 2026 — has shown that this class of chip can eliminate the instruction-fetch stalls that consume up to 96.9% of micro-instruction cycles in conventional accelerators, an efficiency margin that partially compensates for older process nodes.

Beijing has already committed to this playbook

Dongfang Suanxin is not the vanguard — it is the second wave. Huawei is the first. Satellite imagery obtained by the Financial Times showed three semiconductor plants under Huawei's control in the Guanlan district of Shenzhen, including facilities operated by memory-chip maker SwaySure and equipment maker SiCarrier — both added to the US Entity List in December 2024. Dylan Patel of SemiAnalysis told the FT that "Huawei has embarked on an unprecedented effort to develop every part of the AI supply chain domestically… we have never seen one company attempt to do everything before." A Merics study of the resulting supply-chain conglomerate argued that Huawei is developing into a Samsung-style chaebol, with Hubble Technology Venture Capital having invested in 28 semiconductor-related enterprises in 2021 alone — a keiretsu Dongfang Suanxin's backer list clearly overlaps.

In late May 2026, Huawei formalized the intellectual case with what it calls the "Tau Scaling Law" — an engineering doctrine that treats 3D architectural innovation as substitutable for transistor shrinks, per SCMP's reporting. Huawei's CloudMatrix 384 supernode, described in an August 2025 Huawei Cloud technical report, already delivers 2,400 tokens per second per Ascend 910C chip at roughly 50 milliseconds time-per-output-token by exploiting globally pooled HBM across 384 chips connected by an ultra-high-bandwidth UB fabric. That is Nvidia GB200 NVL72-class inference performance built on a 7nm SMIC process node. The packaging is doing the work the lithography cannot.

Dongfang Suanxin fits into that industrial architecture as the merchant-market complement. Huawei sells vertically to Chinese cloud operators willing to accept its stack; the DF1000 is being positioned to integrate with third-party domestic AI servers — the Inspur, Sugon, and H3C boxes that populate provincial data centers. If it works, it closes the last non-Huawei gap in China's domestic AI hardware supply chain.

Washington's control regime is drifting the other way

The uncomfortable context for the DF1000's debut is that US policy is loosening, not tightening. The Congressional Research Service, in its update on advanced semiconductor controls, catalogued a sequence of Trump-administration reversals: rescission of the January 2025 AI Diffusion Rule in July 2025, resumption of H20 licensing, restoration of Electronic Design Automation software sales to China (in exchange for Beijing resuming rare-earth-magnet licensing), and a July 2025 AI Action Plan that pivoted from restriction to promoting "US full AI technology stack" exports to allied countries. On September 2, 2025, BIS published a final rule removing Intel Semiconductor (Dalian), Samsung China Semiconductor, and SK hynix Semiconductor (China) from the Validated End-User program effective December 31, 2025 — a hardening on the memory side that coexisted, awkwardly, with a softening on the logic side.

The clearest signal came in April 2025, when the Trump administration first banned Nvidia's H20 chip and then reversed within weeks. Nvidia had disclosed the initial curbs would cost the company $5.5 billion, according to Al Jazeera; in the first quarter of 2025 alone, leading Chinese tech firms had purchased $16 billion of H20 chips in anticipation of a ban, according to NPR's reporting. In August 2025, the White House announced Nvidia and AMD would remit 15% of Chinese chip-sales revenue to the US Treasury — an arrangement the BBC reported as a first-of-its-kind revenue share on export licenses, and one that Representative Raja Krishnamoorthi called a validation that "export controls work, and we don't have time to waste."

For Chinese planners, this creates a two-front strategic problem that Dongfang Suanxin is engineered to solve. Front one: the H20 is back in the market at scale, meaning domestic chips must be commercially competitive, not merely available under duress. Front two: the controls that remain — particularly the FDP rule on HBM and the Entity List additions of SiCarrier and SwaySure — still bite on any design that copies Nvidia's HBM-centric architecture. A 3D near-memory design finesses both problems. It does not need HBM. And because it is software-defined, one SKU can absorb workloads Nvidia currently splits across multiple part numbers, dramatically improving fab-capacity economics on SMIC's 7nm N+2 line.

Beijing has begun using its own mirror-image toolkit as well. The Center for Security and Emerging Technology documented China's July 2025 revision of its Catalogue of Technologies Prohibited or Restricted from Export, which under control point 083906X restricts outbound transfer of core hardware manufacturing techniques for supercomputers exceeding 97 trillion operations per second. The chip war is now bidirectional, and China is beginning to protect the packaging IP that gives designs like the DF1000 their edge.

The commercial and industrial stakes

The DF1000 is not, on any credible read, a finished product yet. Windows News, which surveyed the company's technical disclosures, described the design as "far from a finished product" and stressed that yield economics on hybrid-bonded 3D stacks remain unproven at commercial volumes, per Windows News. Thermal density is the standing problem: 3D stacks concentrate heat vertically, and Chinese fabs lack some of the advanced cooling and thermal-aware floorplanning IP that leading-edge Western designs deploy — a constraint mapped in detail by Kurshan, Reinman, Cong and collaborators in an arXiv survey of fine-grain 3D integration that showed peak-temperature management remains the binding constraint on multi-layer stacks.

But even a partial success re-prices the market. If the DF1000 delivers usable inference throughput at, say, 60–70% of an H20 at similar power, Chinese hyperscalers gain a domestic option they can specify without export-license risk — and Nvidia's China revenue, currently underwritten by the 15% Treasury remittance deal, becomes politically harder to defend at home. The historical parallel that matters is not the 1980s US-Japan chip war but the 2010s US-China 5G contest: Washington restricted, Huawei substituted, and the substitution reshaped global infrastructure procurement in ways US policy did not intend and cannot easily undo. The Merics analysis called that pattern "self-reliance in key and core technologies." The DF1000 is what self-reliance looks like when it graduates from telecoms to AI silicon.

The named beneficiaries are legible. CXMT, China's DRAM national champion, gets a domestic customer that does not require HBM3E — a market its capacity can serve today. SMIC gets a design partner willing to specify its N+2 process. Xiaomi and JD.com, through their venture arms, get option value on a chip that could displace Nvidia inside their own data centers. Yunfeng Capital continues its transition from consumer-internet plays into hard tech. The named losers are equally legible: Nvidia loses long-run pricing power in China even as its short-run H20 revenue holds; Samsung and SK Hynix lose a Chinese HBM market they had already been substantively cut out of; and BIS loses another rung of leverage as the design space its rules were written to constrain shifts sideways into packaging.

Diplomat View

The bet worth making is that Dongfang Suanxin will ship a DF1000 that lands commercially between an Nvidia A100 and H100 on inference workloads by late 2027, and that this will be sufficient — combined with Huawei's Ascend line — to make Chinese hyperscalers 60% domestic-chip by 2028. That forecast rests on three conditions: CXMT hitting DDR5-class yields at volume, SMIC's N+2 line sustaining 20,000 wafers per month, and no US move to control advanced packaging equipment directly. The falsification test: if BIS adds hybrid-bonding tools from Applied Materials, Besi, and Tokyo Electron to the Entity List's controlled category, the calculus shifts and Dongfang Suanxin's timeline slips by 18–24 months. What would revise the call the other way: a credible DF1000 tape-out disclosure before Q2 2027, or state procurement mandates forcing Chinese cloud operators to specify domestic chips at a fixed share of new capacity.

Watch:

• October 2026 US Commerce semi-annual review — whether packaging equipment moves into the controlled category.
• CXMT HBM2E capacity announcement (expected H2 2026) — the memory-side gating factor.
• Dongfang Suanxin's first DF1000 tape-out disclosure — the technical proof point that separates announcement from product.

The Bottom Line

Dongfang Suanxin's debut matters not because a single startup will beat Nvidia, but because it confirms that Beijing's chip strategy has quietly shifted from chasing lithography to owning packaging — a domain where US controls are weaker, Chinese equipment is closer to parity, and one clever design can absorb workloads Washington's rules were written to segment. If the DF1000 ships anywhere near its promise, the export-control regime built on transistor-density and HBM thresholds will look, in hindsight, like the Maginot Line of the AI age: technically formidable, strategically bypassed.